Hello,

I have designed and implemented a eth-mac and interfaced it to the
national DP series phy. The performance of the mac was alright. The
pupose of designing the mac was to make an ethernet packet encryptor.

What the mac will do is recieve a packet and decapsulate it. It will
store the packet header in a fifo and send the packet data to the core
for encryption. It will then recieve the encrypted packet data from the
core and then encapsulate the packet with the header and transmit it.

The issue that I am having is that I need to optimize my design clock
cycle wise so that the delay induced by this design on the ethernet
connection is minimum. I have optimized the aes core to the max. Now I
need to optimize the mac. Please give me a few guide lines or tips on
how to cut down on clock cycles in the eth-mac

I will appriciate your help very much

regards

Sajjad